ARM (NOT thumb), 16 bytes excluding return instruction
Second, entirely different answer, still 4 instructions though.
Machine code:
01 10 80 e3 01 00 80 e0 e0 80 00 01 e3 f0 10 00
This one, unlike my Thumb submission, is entirely different in that it is byte reversible (hence why it is split in 8 bits instead of 32 bits)
It happens to do basically the same thing, though, add 1 on forwards and -1 on backwards.
Forwards:
movs r1, #1
add r0, r0, r1
smlatteq r0, r0, r0, r8
andseq pc, r0, r3, ror #1
Backwards:
movs r1, #-1 @ a.k.a. mvns r1, #0
add r0, r0, r1
smlatteq r0, r0, r0, r8
tsteq r0, r3, ror #1
You may be asking yourself, "smlatteq
? andseq
? tsteq
? What the **** do those do?"
The answer is nothing unless the zero flag is set.
This code heavily abuses ARM's conditional execution and "s" instructions.
movs
will set the condition flags on the value it sets (why this exists for the immediate form, I will never know). I set them to 1 on forwards, and -1 on backwards. These are both non-zero, so they clear the zero flag.
We also use the version of add
which does not update the flags, so the zero flag remains clear.
Therefore, since the zero flag is not set, all instructions with the eq
suffix will be ignored.
And that is a VERY good thing, because ands pc, r0, r3, ror #1
would almost certainly crash the program (it would jump to a garbage address)
Therefore, in terms of what is effectively executed, it is this:
Forwards:
movs r1, #1
add r0, r0, r1
nop
nop
Backwards:
movs r1, #-1 @ a.k.a. mvns r1, #0
add r0, r0, r1
nop
nop
Similar to my Thumb answer, you can repeat these as much as you wish, but you must put a bx lr
(e12fff1e
) at the end, and it is called with r0 == 0
.
aBBaaBBa
? \$\endgroup\$0+1-0
as a Python solution, relying on the interpreter to implicitly print out the result of an expression formed by concatenating that or its reverse some number of times. \$\endgroup\$0+1-0
is a great idea for an answer. You just need to pick the right language, e.g. tio.run/##y0osKPn/30DXUNvg/38A \$\endgroup\$