Timeline for Build a multiplying machine using NAND logic gates
Current License: CC BY-SA 3.0
10 events
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| Apr 13, 2017 at 12:39 | history | edited | CommunityBot |
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| Aug 10, 2013 at 14:26 | comment | added | boothby | Most excellent! | |
| Aug 10, 2013 at 11:27 | history | edited | John Dvorak | CC BY-SA 3.0 |
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| Aug 10, 2013 at 10:33 | history | edited | John Dvorak | CC BY-SA 3.0 |
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| Aug 10, 2013 at 10:26 | history | edited | John Dvorak | CC BY-SA 3.0 |
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| Aug 10, 2013 at 8:07 | history | edited | John Dvorak | CC BY-SA 3.0 |
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| Aug 8, 2013 at 14:16 | vote | accept | Joe Z. | ||
| Aug 12, 2022 at 0:30 | |||||
| Aug 8, 2013 at 13:51 | comment | added | Joe Z. | I tried to make this exact network last night, but I'm not well-versed enough in logical networks, it seems. | |
| Aug 8, 2013 at 9:32 | comment | added | Peter Taylor | The only part which looks potentially optimisable is the middle block of adders. The logical requirement is for a superfull-adder (takes 4 input bits, has two carry output bits) and a full adder; your implementation with two full-adders and two half-adders looks hard to improve. | |
| Aug 8, 2013 at 8:06 | history | answered | John Dvorak | CC BY-SA 3.0 |