Chip, 80 bytes
AZ BZ CZ DZ EZ FZ GZ HZ
,[',[',[',[',[',[',[',['*Z~S
`--)--)--)--)--)--)--)~aef
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Takes input as two consecutive bytes. (In the TIO, the characters 'A' and '$' are used, corresponding to values 65 and 36.)
This solution has eight chunks, one per bit, plus an extra chunk at the end. Looking at these chunks:
A
is bit 0x01
of the input. (The letters A
though H
correspond to a bit each.) Z
holds on to a value for the next cycle while producing the previous value. Hence, A
and Z
are the current and previous values of bit 0x01
.
[
is an AND-gate; it simply ANDs its two inputs together. So the full row of such gates is performing a bitwise AND of the two bytes.
Finally, )
is an OR-gate. All eight AND results are OR'd together, giving us a True is there is a match, and a False otherwise. We want the inverse of that, so use a NOT-gate (~
) before passing it to the output.
We output via a
, e
, and f
. The a
, which corresponds to bit 0x01
of the output, receives the result of the above computation. The other two bits e
and f
are unconditionally on, together forming 0x30
. Therefore, the output is either 0x30
or 0x31
, which are the codes for ASCII characters '0' and '1'.
The extra stuff is housekeeping, it prevents output for the first cycle (there is no previous value at this point, so there is no reason to do a comparison).
Alternate solution, also 80 bytes
A~.B~.C~.D~.E~.F~.G~.H~.
Z~<Z~<Z~<Z~<Z~<Z~<Z~<Z~<*Z~S
a[--[--[--[--[--[--[--'ef
This is very similar in style, but uses a different algorithm. Where above we AND each pair of bits, and use OR to reduce the result to a single value, here we OR the negation of each pair of bits, then use AND to reduce.
One thing to note: we use an implicit OR here, instead of a proper gate as above. We could have used implicit OR'ing above as well, but there is no byte-savings there.