Write a proper quine whose every rotation is itself a proper quine.

For example, if your source code is abcdef, then:

  • abcdef would output abcdef
  • bcdefa would output bcdefa
  • cdefab would output cdefab
  • defabc would output defabc
  • efabcd would output efabcd
  • fabcde would output fabcde

A rotation "is made by splitting a string into two pieces and reversing their order".


This is . Shortest answer in bytes wins. Standard loopholes apply.

  • \$\begingroup\$ So I could have program aaabbb and I could say that the next rotation is bbbaaa? Or would the next rotation have to be baaabb? \$\endgroup\$ – Beta Decay May 19 '17 at 9:30
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    \$\begingroup\$ The next rotation is baaabb. \$\endgroup\$ – Leaky Nun May 19 '17 at 9:31
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    \$\begingroup\$ Side note, the standard Fission quine is a different quine of rotation-safe: no matter how you rotate it, it will always print the original source code. \$\endgroup\$ – Martin Ender May 19 '17 at 9:45
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    \$\begingroup\$ If a quine in a language is one byte, is that cheating? \$\endgroup\$ – MD XF May 29 '17 at 4:41
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    \$\begingroup\$ Is this a proper quine? \$\endgroup\$ – tsh Sep 5 '17 at 5:50

Motorola MC14500B Machine Code, 1 byte

The 1 byte score is derived from two 4-bit instructions:

0000 0010


The Motorola MC145008 is a single chip, one-bit, static CMOS processor optimized for decision-oriented tasks. The processor is housed in a 16-pin package and features 16 four-bit instructions. The instructions perform logical operations on data appearing on a one-bit bidirectional data line and data in a one-bit accumulating Result Register within the ICU. All operations are performed at the bit level.

The pins of the processor are numbered:

Pin assignment

Instructions are presented to the chip on the 4 instruction pins, (I0, I1, I2, I3), and are latched into the Instruction Register, (IR), on the negative-going edge of X1.

In layman's terms, pins 4 through 7, are used to present the Instruction Register with an instruction, but the bits are interpreted in the reverse order. For example, the instruction 0001 would have pin #7 in the high state and pins 6 through 4 in the low state.

The instructions, are decoded in the Control Logic (CTL), sending the appropriate logic commands to the LU. Further decoding is also performed in the CTL to send a number of output flags (JMP, RTN, FLGO, FLGF) to pins 9 through 12. These are used as external control signals and remain active for a full clock period after the negative-going edge of X1.

Or, put simply, pins 9 through 12 are the output flags FLGF, FLGO, RTN, and JMP, respectively. Note that data is typically multiplexed to the WRITE pin (pin #2). The output flag pins are similar to other language's exit codes.

Each of the ICU's instructions execute in a single clock period.


Initial position

0000    NOPO
0010    LDC

The clock periods:

  1. The NOPO instruction puts pin #10 (FLGO) in the high state. Before the next clock period, the output flag pins are put back into the low state.
  2. The LDC instruction loads the complement of the Data Bus' value to the Result Register, without affecting the output flag pins.

So, during the program's two clock periods, the output flag pins have represented 0100 0000, which, read in reverse (like the input pins), is 0000 0010, or the original instructions.

First rotation

0010    LDC
0000    NOPO

The clock periods:

  1. The complement of the Data Bus is loaded to the Result Register, with no effect of the output flag pins.
  2. Pin #10 in switched to the high state.

During these two clock periods, the output flag pins have represented 0000 0100, which, when reversed, are the instructions 0010 0000.


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