The 1 byte score is derived from two 4-bit instructions:
The Motorola MC145008 is a single chip, one-bit, static CMOS processor optimized for decision-oriented tasks. The processor is housed in a 16-pin package and features 16 four-bit instructions. The instructions perform logical operations on data appearing on a one-bit bidirectional data line and data in a one-bit accumulating Result Register within the ICU. All operations are performed at the bit level.
The pins of the processor are numbered:
Instructions are presented to the chip on the 4 instruction pins, (
I3), and are latched into the Instruction Register, (IR), on the negative-going edge of X1.
In layman's terms, pins 4 through 7, are used to present the Instruction Register with an instruction, but the bits are interpreted in the reverse order. For example, the instruction
0001 would have pin #7 in the high state and pins 6 through 4 in the low state.
The instructions, are decoded in the Control Logic (CTL), sending the appropriate logic commands to the LU. Further decoding is also performed in the CTL to send a number of output flags (
FLGF) to pins 9 through 12. These are used as external control signals and remain active for a full clock period after the negative-going edge of X1.
Or, put simply, pins 9 through 12 are the output flags
JMP, respectively. Note that data is typically multiplexed to the
WRITE pin (pin #2). The output flag pins are similar to other language's exit codes.
Each of the ICU's instructions execute in a single clock period.
The clock periods:
NOPO instruction puts pin #10 (
FLGO) in the high state. Before the next clock period, the output flag pins are put back into the low state.
LDC instruction loads the complement of the Data Bus' value to the Result Register, without affecting the output flag pins.
So, during the program's two clock periods, the output flag pins have represented
0100 0000, which, read in reverse (like the input pins), is
0000 0010, or the original instructions.
The clock periods:
- The complement of the Data Bus is loaded to the Result Register, with no effect of the output flag pins.
- Pin #10 in switched to the high state.
During these two clock periods, the output flag pins have represented
0000 0100, which, when reversed, are the instructions