This is "programming" at its most fundamental.

Build a diagram of (two-wire) NAND logic gates that will take the input wires A1, A2, A4, A8, B1, B2, B4, B8, representing two binary numbers A to B from 0 to 15, and return values on the output wires C1, C2, C4, and C8 representing C, which is the sum of A and B modulo 16.

Your score is determined by the number of NAND gates (1 point per gate). To simplify things, you may use AND, OR, NOT, and XOR gates in your diagram, with the following corresponding scores:

  • NOT: 1
  • AND: 2
  • OR: 3
  • XOR: 4

Each of these scores corresponds to the number of NAND gates that it takes to construct the corresponding gate.

Lowest score wins.


03-07 19:09: Due to discussions with Jan Dvorak, it came to my attention that the total number of gates, constants and splits is always determined solely by the number of gates. Because of this, I have simplified the score requirement back down to simply the number of gates required.

  • 2
    I don't think you can get much better than the classic full-adder design. – Mr. Llama Mar 7 '13 at 20:52
  • That uses AND, OR, and XOR gates and would have a score of 29 per digit (minus a few for carrying in the end cases). Can you condense it into using fewer NANDs? – Joe Z. Mar 7 '13 at 21:08
  • Are multi-wire NANDs allowed? – John Dvorak Mar 7 '13 at 21:14
  • @JanDvorak Not sure what a multi-wire NAND is. – Joe Z. Mar 7 '13 at 21:17
  • 1
    They are quite standard. It emits true if any input is false. – John Dvorak Mar 7 '13 at 21:26
up vote 7 down vote accepted

31 gates

full adder

[created in Logisim]

The standard XOR-gate can be built with four NANDs. Tapping the first NAND provides us with a fairly compact half-adder with inverted carry:

hadder(A,B) => (sum, iCarry):

X = A^B   

sum = (A^X)^(B^X)
iCarry = X

These can be combined into a 9-gate full adder:

fadder(A,B,C) => (sum, carry):

DD1 = hadder(A,B)
DD2 = hadder(DD1.sum, C)

sum = DD2.sum
carry = DD1.iCarry ^ DD2.iCarry

These combined yield a naive 36-gate four-bit adder. Not bad.

Now, we inline all modules and perform these optimizations:

delete gates with no output (only the final gate)
0^x => 1                    (one gate, twice)
1^(1^x) => 0                (two gates, once)

for a grand total of 31 gates.

Note that the count of splits and NAND-gates are intimately connected: Each 2-input NAND (larger are explicitly forbidden) takes two inputs and produces one output. Each 2-way split (let's assume larger splits are forbidden) takes one input and produces two outputs. Also, there are no unused outputs or floating inputs (let's assume constants are not allowed). If there are N more inputs than outputs, there must be N more NANDs than splits.

Thus, a 31-NAND 8=>4 module will neccessarily have 27 2-way splits.

Here are the split cardinalities for the above adder just in case larger splits are allowed:

18x wire (no split)
  4x output
  14x XOR 2nd stage
16x 2-way split
  8x input
  6x H2 input
  2x last bit XOR 1st stage
4x  3-way split
  4x XOR 1st stage
1x  4-way split
  1x 1st bit XOR 1st stage; if constants are alloweed; this is a three-way split
  • The 27 splits each count as 1 point, so your total score is actually 58. – Joe Z. Mar 7 '13 at 23:57
  • @JoeZeng as I elaborated, if you count my diagram as 27 splits (2-way only, constants not allowed), then #splits = #gates - 4 – John Dvorak Mar 7 '13 at 23:58
  • So basically, the score only has one degree of freedom among the number of gates and the number of splits? – Joe Z. Mar 8 '13 at 0:00
  • Yup. Unless you allow constants. – John Dvorak Mar 8 '13 at 0:01
  • If I allow constants at 1 point each, will that affect anything? – Joe Z. Mar 8 '13 at 0:03

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